Here it's the mail, untouched:

Da: crucsupport@micron.com
Data: Mer 26 Ott 2005 18:36:06 Europe/Rome
A: <costri@twtnet.com>
Oggetto: RE: Re: Regarding the SPD EEPROM used on DIMMs.

The memory will synchronize and all modules will run at the same speed. For example if you have a motherboard with 1 module running at DDR333 cl2. Then you install a module that is DDR400 cl3, the SPD chip on the modules will work with the bios of the motherboard to run at slower speed. In this case DDR333 cl3. In most cases you can go into the bios and change the cl timings to match if needed. Hopefully this answers your question.


ADAM VALADEZ
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-----Original Message-----
From: Costantino
To: crucsupport
Subject: Re: Regarding the SPD EEPROM used on DIMMs.

Thank you for your automatic response, but it does not address my query.
I already know what an SPD EEPROM is, how it works and where it is usually placed on a TSOP SDRAM module.

My question is:
Do modern Memory Controllers, which address DDr SDRAM modules, adapt their timing parameters to address them the same way they used to do with simple SDRAM modules?

For example: an Apple PowerMac G4 system employing 100MHz or 133MHz single SDRAM modules employing the UNI-North IC Memory Controller which used to get its timing parameters by reading the SPD EEPROM placed on the FIRST SDRAM module found along the RAM expansion slots, ignoring the readings on the other eventual SDRAM modules present onto the subsequent RAM slots.
It is thus questioned, weather more recent motherboard engineering and/or Memory Controllers, employing/addresing 184-pin DDR SDRAM modules, are capable to adjust their data addressing parameters by reading ALL the SPD informations held by ALL the modules present on the RAM expansion slots.

If so, what parameters are used?
The Memory Controller is capable to assess the "worst" timing scenario it finds (independently from the modules' position along the expansion bays) and adjust its timing parameters consequently?

Thanks for any and all responses.

Yours sincerely.

Costa
O.K., then it seems to me that it's Apple's firmware/ROM which during the booting sequence "reads" all the SPD EEPROMs present along the RAM expansion rails.
Then it does an "averaging" by selecting all slowest parameters and hands them over to the Memory Controller for operations.
Could that be it?

TZ, what do you make of it?
More questions to put to ADAM VALADEZ?

Let me know.

Ciao.

Costa.