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Thread: SDRAM Memory FAQ

  1. #1
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    Lightbulb Memory Reference

    Memtest
    - command line utility to test 'most' of the available memory (but not all). Can be run in Single User Mode and test all but about 60MB RAM.

    Rember
    - GUI version of memtest (4.05 currently) Download
    http://www.memtestosx.org/
    Disk Test (Hard-Diskcorruption_test Folder.sit). http://www.gballard.net/macrant/ram.html
    http://www.macintouch.com/g5reader07.html#jan08

    MacIntouch BAD RAM Report
    More about reseat RAM, using a pencil eraser to clean contacts, and to be careful when installing RAM in G5s.

    DIMM First Aid
    DIMM First Aid 1.2 on Version Tracker

    - A great explanation of why and what SDRAM specs and Apple's G4 firmware are all about, with note about chips per bank, and compatible systems (only for PC100/133, not compatible with DDR or PC2100 or later).

    DFA was developed after Apple G4 firmware update started requiring the SPD code be present in order to be used. If SPD is present, DFA returns "OKAY" otherwise it will try to "repair" or not present, as well as tell you what is found.
    Don't take "OKAY" as meaning it passed any other testing.

    MacInTouch "Bad RAM?"
    Crucial Library
    Crucial Memory Glossary
    Crucial FAQ
    Crucial: Apple Selection Guide

    Ars: Understanding Latency and bandwidth

    <UL TYPE=SQUARE><LI>How RAM works
    <LI> Simmtester.com: Understanding DDR Serial Presence Detect (SPD) Table
    <LI>Crucial Technologies Support page
    <LI> Crucial KB
    <LI>Kingston Technology's Ultimate Memory Guide
    <LI>Micron Technology DRAM Product Guide
    <LI>Samsung Semiconductor's Support web page
    <LI>How Stuff Works: DDR RAM
    <LI>Tom's Hardware Guide: DDR SDRAM
    </LI>
    http://www.apple.com/support/ibook/
    iBook Upgrades
    PDF Manual: Adding RAM Customer Installable Parts
    iBook Specification
    iBook Discussions
    SO-DIMM specifications

    G5 Memory Specs Apple KB #86414
    Apple's PDF on G5 Memory
    Apple Discussions: biggest thread on G5 memory

    PPCNUX - Memory Performance Benchmark
    System Profile should show if they are working as one.
    I assume it enables DDR or 128-bit vs 64-bit.
    G5 test bus utility download
    iMac G5 RAM Upgrade
    MacMini RAM Expansion

    Apple Tech Note QA1191 PC2700 in MDD
    PowerMac G4 Dev Note

  2. #2
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    Lightbulb

    From the Gurus Memory Guide: <BLOCKQUOTE class="ip-ubbcode-quote"><font size="-1">quote:</font><HR>Yosemite/Yikes/Sawtooth/improved iMac SDRAM DIMMs are PC100-compliant, 3.3v unbuffered pieces with a rating of 125MHz/8ns or faster.

    Though 100Mhz/10ns SDRAMs for Apple Beige G3 may physically fit in Yosemite, Yikes, Sawtooth or iMac, Apple advises against attempting to use them. Beige G3 SDRAM is typically too slow for the 100MHz logic board buses in these machines.

    Note: All 168-pin PC100 SDRAM DIMMs listed on this page are high-quality 3.3-volt, unbuffered "2-2-2" SDRAM, fully PC100-compliant, 64-bit-wide, with a speed of 125MHz/8ns or faster. These SDRAM DIMMs feature a properly programmed 256-byte Serial Presence Detect ROM for perfect compliance with Apple specifications. Two inches in height (or less), these SDRAM DIMMs have been specifically engineered for use in Yosemite, Yikes G4, and original Sawtooth, and incorporate 64 Mbit parts in 32MB and 64MB pieces, and 128 Mbit parts in 128MB and 256MB pieces. (Low-profile Sawtooth 256MB SDRAM is 1.25-inches in height, and appropriate also for improved iMac, aka iMac DV.)

    Apple Power Macintosh G3 and G4 released before January, 2001 are compatible with 3-2-3, 3-2-2, and 2-2-2 PC100 speed codes, though MacGurus ships only genuine 2-2-2 SDRAM for enhanced compatibility with G4 processor upgrades which are entering distribution channels at this time and to optimize memory bandwidth and performance. While Yosemite, Yikes and the original Sawtooth query the presence detect ROM for memory timing settings of all memory installed, and throttle down for compatibility with the slowest installed device, mixing speed types generally inflicts only a minor performance penalty.

    Acme Memory SDRAM is not adversely affected by Apple's Firmware Update 4.1.8, which disables SDRAM with incorrectly programmed serial detect EEPROMs. If you would like to test your memory for compatibility, Glenn Anderson's DIMMCheck and DIMM First Aid are available on our FTP site, along with several other memory testing utilities. Acme PC133 SDRAM is engineered to support both the 133MHz clock and MaxBus protocol of the improved Sawtooth logic board.

    BeigeMT:

    Yes, you can use most PC100 and PC133 SDRAM in minitower (MT) revisions of the Beige G3, and it does generally work well with G3 and G4 processors, including dual-G4's, running at 500MHz and faster. Acme PC133 G3/G4 SDRAM in densities up to 256MB is compatible with G4 upgrades from third-party manufacturers installed in MT Beige G3. We have confirmed that 512MB SDRAM DIMMs are not compatible in beige G3. The max configuration for beige G3 is 756MB, attained using three 256MB SDRAM DIMMs. Larger 512MB SDRAM DIMMs will not work in Gossamer or Artemis logic boards.
    SDRAM Guide <HR></BLOCKQUOTE>
    Costa in Beige G3 thread:I would double on all TZ wrote to you. However, let me summarise:
    • What Crucial has to say about upgrading different Beige G3 revision machines, is now out of date.
    • In short, whatever revision ROM/Logic Board Beige G3 you have, it will *NOT* inhibit your ability to increase/upgrade your RAM availability.
    • The ROM/Logic Board revision issue is totally indipendent from the relationship there is between your internal Memory Controller and your RAM banks. See this post of mine for further details.

    You can safely fit inside your Beige Desktop Crucial's 256MB sticks an all three RAM expansion rails, thus maximazing your RAM up to 768MB.
    I have only the following reccomendations:
    1. Make sure you buy the "LOW PROFILE" modules, otherwise you will be unable to close safely your Desktop case as the top of the modules will nock on your internal PSU metal cover. You need to choose those modules with maximum hight = 1.125 in. (or 28.58 mm.). However, Crucial knows which kind will suit you.
    2. Crucial will offer you the PC-100, CL2 (9 ns) ones, which are Micron's part # MT16LSDT3264A-10E; they will be just fine for you. Such modules will ALSO allow you, should you want so, to upgrade your CPU and do a Front System Bus overclocking up to 83.33 MHz (from the stock 66.67MHz).
    3. Remember to flash your PRAM, on first re-booting your Mac after having added your new RAM sticks, so as to let your machine "know" about the new RAM availability.
    4. If you max out your RAM up to 756MB, you will notice at first, that your old Beige will take a few minutes longer to boot into the OS splash screen: this is due to the fact that your internal Memory Controller takes a few minutes longer to performe his Memory Test thing during the booting sequence. You can disable the Memory Test at startup, if so you wish, by opening the Memory Control Pannel while you keep the Option+Control keys pressed; an extra window will open up giving you the ability to choose such disabling feature.

  3. #3
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    Lightbulb SDRAM for Beige, B&W G4 Upgrades

    Blue & White G3 Memory: a definitive answer?

    Knowledge Base Article 58182 Yosemite Memory Upgrades.

    Essential reading for Beige G3 and others as well. Thread on Apple Discussion: Blue G3: Expansion. With comments and insights by OWC's Larry O'Conner. (Apple thread no longer available.)

    I've read from prominent sources that DIMM First Aid is unreliable (the only thing users have sometimes when dealing with memory vendors and resellers when they are shipped PC66 when they order PC100 or something). If DIMM First Aid (1.2) was/is unreliable, I'd expect there to be a warning note. Also, TattleTech provides detailed information on memory as well (shareware, requires registration to unlock all the features).

    If you plan to upgrade a Beige G3/233 with one of the G4/1000 cpu upgrades, you might want the best memory you can use (and before prices get even higher, though they are still under what they were 3 yrs ago).

    A G4 has the ability to push memory at 164MB/sec. Solid. The G3 would begin at 99MB/sec but fall off to 85MB/sec. So G4 requires better quality and higher standards. The B&W always required memory to run at 125MHz (which translates into 8 ns). Some PC133 memory works in 100 MHz front side bus. (That is buried in there somewhere, and is the only time or reason why G4 makes a difference.)

    In a Beige, the FSB can be anywhere from 66 - 83MHz, and G4 is going to result in 1.64x factor of memory thruput. So at 66 MHz you are looking at 108MB/sec. Which is slightly above the 10 ns of some SDRAM that is sold as PC100, and quite a bit more than originally supported in Beige. You NEED a minimum of 8 ns for Beige G4 is what I learned the hard way. The same memory sold by Crucial for Yosemite has always worked flawlessly. just as MacGurus, which is often Samsung but not always. (Samsung sometimes supplies Micron or Crucial with RAM to help meet demand.)

    OS X 10.3.x also uses RAM more, puts more demands, and any flaw or error is going to surface. The B&W can't take advantage of mixed CAS Latency either.

    SDRAM comes in three flavors:

    * PC100 G3 SDRAM for Apple Power Macintosh G3 "Beige," aka Gossamer and Artemis.

    You may see some PC66 SDRAM sold also, as well as PC100 10 ns. as well as 8 ns. It is MY experience that Beige G3 and you will be better off with PC100 8 ns - memory designed for Yosemite - but avoid trying to use PC133.

    * PC100 SDRAM for Apple Power Macintosh G3 "Blue and White," aka Yosemite; Apple Power Macintosh G4 PCI "Graphite," aka Yikes; Apple Power Macintosh G4 AGP "Graphite" aka Sawtooth; Power Macintosh G4 Multiprocessor, aka Sawtooth; Power Macintosh "Cube," and Apple iMac, iMac DV and iMac DV Special Edition, aka AirPort-capable iMac.

    * PC133 SDRAM for Apple Power Macintosh G4 AGP "Digital-Audio," aka Sawtooth. Note that PC133 CL2 (CAS2, 2-2-2) SDRAM is very versatile, and is backwards-compatible with many Power Macintosh including all variants of Airport-capable iMac, Sawtooth, Yikes, Yosemite, and some Beige G3 Gossamer and Artemis.

    More information Continued...

    There is SO MUCH Confusion about RAM!

  4. #4
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    Lightbulb

    DIMM First Aid ver. 1.2
    The above version of DFA was developped using the PowerMac G4 series adopting the UNI-NORTH chipset as memory controller and IC circuit, under OS9.x.

    Due to the above, all previos Mac models using the Motorola MPC106 (a.k.a. GRACKLE), or previous memory controllers chipsets may return a DFA diagnosis stating:
    <BLOCKQUOTE class="ip-ubbcode-quote"><font size="-1">quote:</font><HR> DIMM reads an old or incompatible page number<HR></BLOCKQUOTE> Other than that, the DFA report is correct.
    DFA runs under OS9.1 or later (it won't run properly under OSX).

    DIMM First Aid

    DIMM First Aid is an application for checking and repairing the settings in the SPD EEPROMs on SDRAM DIMMs.

    Send any feedback or bug reports to dfa@mactcp.org.nz

    DIMM First Aid 1.2 is now available. Version 1.2 adds support for the QuickSilver G4, and can now check DIMMs on the Beige G3. Reporting the speed of PC133-222 DIMMs has been fixed. DIMMs that are incompatible with newer Macs are no longer reported as incompatible on the Beige G3 and B&W G3.

    New in DIMM First Aid 1.1: support for the new iBook, can now check DIMMs on the PowerMac G3 B&W and the PowerMac G4 PCI graphics, and reports the speed rating for DIMMs. Version 1.1 also checks for DIMMs that use chips that are incompatible sizes, such as 64Mx4 chips used on single bank 512MB DIMMs and 32Mx4 chips used on single bank 256MB DIMMs.

    Incompatible 256MB and 512MB DIMMs: 256MB DIMMs made from one bank of 16 32Mx4 chips and 512MB DIMMs made from one bank of 16 64Mx4 chips are not compatible with the G4 AGP Graphics, the slot loading iMac, and later models of Mac. They will only work in the Beige G3, the B&W G3, and the G4 PCI Graphics. If you are buying a 256MB or 512MB DIMM and you are not sure if it will work on a Mac, do not buy DIMMs that have a single bank made from 16 chips, make sure it has two banks of 8 chips each, or for 256MB DIMMs one bank of 8 chips or two banks of 4 chips are also OK.

    Incompatible DIMMs may also be identified as having 32Mx4 chips (for a 256MB DIMM) or 64Mx4 chips (for a 512MB DIMM). DIMM First Aid will identify these DIMMs as having an incompatible number of column address bits. DIMM First Aid can not fix these DIMMs.

  5. #5
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    Lightbulb SDRAM Explained

    I thought useful sharing with others my findings about memory modules and how they basically work.

    The information I will discuss in this post, refers mainly to PC-nnn memory modules bearing 168 pins.

    O.k., then, lets start with some basic definitions:
    <UL TYPE=SQUARE><LI>A DIMM is a whole RAM stick; it refers to the sum of the number of DRAMs devices present.
    <LI>A DRAM device is each of those black, "bug-like" chips (usually with 54 "legs" - 27 on each side) soldered on the green TSOP fiber-plastic module. It's inside these little bugs that the real technology resides.
    <LI>A SDRAM module is the whole MacKoy: it refers to all the DRAMs plus the fiber-plastic module and the 168 pins which help it to connect on the RAM expansion rails inside the logic board.
    <LI>The Memory Controller (=MC) is a chip solderd on the logic board. It is responsable, among many other things, to address the RAM banks where the DIMMs are. It keeps on sending continuosly a strobe-like signal to the DRAMs' (columns). [/list]
    In order to explain further terminology, I need to explain how DRAM devices are built and what they contain.
    DRAM devices are built in "wafer" like stacks each one containing a very thin and dense "grll" of semiconductor material.
    Such "grill", if you were to magnify it, would look very much like the squared sheets of a traditional note pad: a continuous intersection of thin (semiconductive) lines distributed in horizontal and vertical parallel lines to form a series of "squares".
    These squares actually form a series of Column and Row intercepts.
    The "very thin" lines of the semiconductor material are currently built to a total average thikness between 0,13 and 0,11 um (micron), depending on which technology the manufacturer decides to build them. Within the next couple of years, manufacturers plan to achieve 0,09 and even 0,07 average thickness of these lines, so as to reach an even greater "squares" density and, thus, a greater total RAM availability per each DRAM device.
    In fatc, each intercept of a Column with a Row, represents a cell, aka RAM address.
    These cells are capable to retain a positive electron charge for a very short period of time (usually expressed in ns = nano seconds).
    The principle of this could be described as the functioning of the sigar/sigarette lighter you have in cars: when you press the lighter button, the car battery starts charging the resistances on the lighter; when these resistances reach a pre-fixed temperature the lighter pops up for you to use it; however, if you wait too long, the resistances on the lighter will soon cool down loosing the necessary temperature to light your cigarette up.
    This is what happens with those "very thin" interceptions (cells) inside the DRAMs: they get charged and, if they are not continuosly re-charged, they loose their "temperature".
    When a cell is charged it will read a binary "1" symbol.
    When a cell is not charged (or looses it's charge), it will read a binary "0" symbol.

    But how do those cells get charged then? They get charged by the Memory Controller.
    As mentioned above, the MC continuosly sends a "strobe-like" signal to the DRAM devices which "illuminates" all the Columns inside the devices.
    The "strobe-like" signal is very much like those "strobo-lights" SCUBA divers use during night dives.
    Accoriding to the duties the MC is called upon, which are dictated by the kind of data which needs to be transferred to and from the DRAM devices, it will successively select which cells need to:
    <UL TYPE=SQUARE><LI>Have their charge refreshed,
    <LI>Be newly charged, or
    <LI>Be left uncharged.[/list]
    All these actions performed by the MC, determine one of the main characteristics of the DRAM devices which, according to how "well" they react to the MC's strobe-like signalling.
    This important DRAM devices' characteristic is called Cache Latency.

    Every time the MC performes the above actions, it does so because it has received an "order" (= query) from the CPU.
    A typicall CPU's order to the MC could be simplified in this sentence:
    &lt;&lt;I have this data held by my cache memory registers: please, check with the DRAM devices if the data on my cache regisrty is still useful for the task I need to elaborate or if I need to replace such data with the data held by the DRAM devices&gt;&gt;
    The cache memory registers are kept on the CPU's backside bus (which is an in-printed electronic circuit communicating directly with the MC).
    The time which takes the MC to performe the above query and to hand over the answer, is called "Cache Latency", as the cache memory registers are awaiting on the MC's reply.

    This is what happens during the "Cache Latency" period:
    <UL TYPE=SQUARE><LI>Identifying each row and column (row address select, or RAS, and column address select, or CAS) - The MC's "strobe-light" illuminates all the CAS addresses and identifies the Rows with the relevant intercepts (cells): this action takes up "n" System Clock Cycles. This action is ALSO referred to as CAS Latency.
    <LI>Keeping track of the refresh sequence (counter) - This is done automatically by the MC each time it starts this sequence you are reading.
    <LI>Reading and restoring the signal from a cell (sense amplifier) - The MC selects the cells which need to be recharged as their current signal (the binary "1") is still pertinent to the data handled and recharges the cell; this action takes up "n" additional System Clock Cycles.
    <LI>Telling a cell whether it should take a charge or not (write enable) - The MC selects new "empty" cells and charges them with a signal (the binary "1") in accordance to the data handled; this action takes up "n" additional System Clock Cycles.[/list]
    So, if you read that a SDRAM module bears a specification called Cache Latency (or CL) of 2-2-2 (for example), it means that with those DRAM devices the MC is capable to performe each of those above listed actions within the next 2 System Clock Cycles.

    We have also learned that CAS Latency is NOT the same as Cache Latency: it is just a part of the latter. It means that the "strobe flash light" takes up to "n" System Clock Cycles to "illuminate" all the Column intercepts on the "squared sheet note pad".

    Antoher SDRAM module specification we read much about is the one called PCnnn, where "nnn" can be numbers such as "100" or "133".
    Those numbers specify the MAXIMUM frequency at which the DRAM devices are guaranteed to operate; i.e.: 100 MHz or 133 MHz.

    A SDRAM module carrying a PC-133 specification does NOT necesseraly operate at that frequency only. In most cases, the DRAM devices soldered onto it are capable to simultaneously operate at different frequencies.

    It is the MC's duty, according to it's programming settings (via the machine's ROM/BIOS), to choose at which frequency use the DRAM devices according to the current duties is called upon.
    If the DRAM devices wouldn't allow the MC to use different frequencies, then all the specs of the DRAM device should meet the worst timing scenario the MC could face.
    Such "worst" scenario should be taylored to each computer sold on the market, depending on it's characteristics; we would end up paying a fortune for our SDRAM modules!!
    This is why most semiconductor manufacturers choose to build DRAM devices capable of running at different frequencies.

    The PC-133 specification JUST indicates the maximum frequency the DRAM device is capable of running at. Full stop, end of story.

    DIMM First Aid is a generic DRAM analyser, which cannot be accurate enough; this for the simple reason that the time which intercours from you clicking the "open application" command and the application actually questioning the MC, it is litterally fluded with a large number of records. Inevitably, the program returns you the average readings. To my little knowledge, there's no accurate app out there which tells you what happens along the Backside Bus each ns that passes away. More accurate readings are performed by TattleTech app, which also return you the CAS Latency provided by the DRAM devices present at the various frequencies used by the MC.

    The MC uses, on G4 machines, frequencies of 100, 125 and 133 MHz, depending on the task it is called upon (the data it has to handle).

    Many keep on asking:
    &lt;&lt;Would I see any performance increase if I was to use SDRAM modules bearing the CL 2-2-2 specification instead of the "lesser" CL 3-3-3 one?&gt;&gt;
    The answer is NO. Unless you have such reflexes capable of sensing the passing by of 2.5 ns (two point five nano seconds).
    However, obviously a DRAM device capable of allowing the MC to use a CL of 2-2-2, will also allow the MC to handle more data, more efficiently. But the difference is too small for a human being to sense it.

    Try to imagine the cache memory registers as a target behind the propeller of a WWI aircraft (the System Clock) and the MC acting like the timing mechanism which allows the bullets (the data) from your machine gun (DRAM devices) to go through the propeller's blades (the tasks held by the CPU) without damaging them.
    The MC will choose the right moment to give the "fire" command and the machine gun (the DRAM devices) are capable to do so within the desired time frame (2 or 3 Clock Cycles).

    The MC fitted on G4 machines can easily handle DRAM devices bearing the CL 3-3-3 specification even if running Panther.

  6. #6
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    Ciao TZ,

    Are you referring to Andrew Cunningham's report?

    IMHO, there always one little factor to take into consideration, especially with those older B&W machines: what kind of Memory Controller do the new SDRAM modules have to cope with?

    Answer: the old Motorola MPC-106, aka GRACKLE!

    Now, those PC133 sticks have probably been built with newer chipsets in mind, were the FSB (Front System Bus) speed is usually 133MHz. Thus, those DRAMs can easely run at:
    * 133 MHz
    * 125 MHz
    * 100 MHz

    But I doubt they would be able to run at anything slower than that with a CAS Latency which the old GRACKLE can handle.

    On those B&W, the GRACKLE will handle:
    * 100 MHz
    * 85 MHz
    * 66.7 MHz

    happely, but I don't think it will even achieve easily the 125 MHz mark.

    Remember that the GRACKLE is NOT a true 32-bit data bandwidth MC; it is more like a 16+16-bit working bandwidth and, thus, needs a quick response from those DRAMs in order to meet the proper timing on those Chache memory registers.
    Thus, it needs a CAS Latency value of 2 at least at the 100MHz frequency.

    Also, it needs DRAMs capable to return a refresh sequence within the following 8 ns (as you surely know).

    It would be nice to see if those modern SDRAM modules are tested for lower frequencies, so as to give the GRACKLE more opportunities to work.

    "Bad RAM" needs always to be related to the "chipset" and bus ratings it has to cope with. Many times even RAM vendors don't know what DRAMs are made them available form manufacturers, as they don't usually have the time to go through the DRAMs specification data sheet, like we do.

    Just my 2¢ worth.

    Costa

  7. #7
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    Lightbulb Apple Memory Guide Aug 1999

    Apple had a monthly pdf "Memory Guide" back in 1999. The July/Aug edition was the last to list RAM requirements for B&W as being "125 MHz, 8 ns." as after that, they changed it to read 8 nanoseconds.

  8. #8
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    Lightbulb BAD RAM: memory testing methods

    [Sam Herschbein] In the old core memory days, memory diagnostics were designed to test the bit matrix and supporting electronics for electro-magnetic interference. The coders knew the number of wires for the sides of the matrix and how they translated to memory addresses. The tests were then designed to cause the maximum amount of interference possible. When running memory diagnostics, you would hear the memory board's noise change during the different phases of the tests. [...]

    Today, common memory module tests operate sequentially through memory, thrashing bits with selected patterns at a given address and then stepping to the next sequential address. This will not be likely to find most errors generated by electro-magnetic interference.

    Assuming my scenario is valid: A newly modified piece of the OS [e.g. Panther] has the particular bit and memory address read/write pattern(s) that cause electro-magnetic interference errors in a particular module/chip set.
    <BLOCKQUOTE class="ip-ubbcode-quote"><font size="-1">quote:</font><HR> Jeff Bagby shared some more notes about static discharges, memory problems and serious issues for computer reliability:

    On Ric's comment that his PowerBook Pismo G3 may have RAM that deteriorated over the years, I recall that Apple in the past really hammered home the problems caused by static discharge.

    In a video tape as part of my Apple Service training 12 years ago, Steve Wozniak discussed how damage caused by static electricity could take years to manifest itself noticeably. In the tape, he (and I think he is the one who made the following point) said that if you can feel a static pop, it is at least 3,000 volts (but low amperage).

    A discharge of only 10 volts, however, can destroy or damage a logic circuit.

    Make sure you are well grounded, and wearing only natural fiber (non wool) clothing (no synthetics) anytime you open a computer or handle any components.

    [While I always follow those precautions when opening or modifying a computer, I didn't expect such serious problems would be caused just by using a laptop in a low-humidity environment, but I think static discharges through the keyboard likely caused the slow deterioration of the memory card. I subsequently replaced the top card - just under the keyboard, while retaining the lower card, and no problems appeared while running Apple's Hardware Test CD. -Ric Ford] <HR></BLOCKQUOTE>
    Sound familiar? <BLOCKQUOTE class="ip-ubbcode-quote"><font size="-1">quote:</font><HR>If your computer is having persistent stability problems, it may be bad RAM. Now that Windows is a bit more stable than it was back in the bad old days, Microsoft would like to give users a way to point the finger back at their own hardware if their computer is acting up. It released a memory diagnostic utility yesterday. Windows Diagnostic Utility <HR></BLOCKQUOTE>

  9. #9
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    Lightbulb

    Mis-programmed SPD is most likely a major factor in RAM incompatibility. Perhaps there is a way to over-ride RAM settings in Open Firmware (similar to changing BIOS) which can be used to reduce how much physical RAM is seen in a system, not sure about changing SPD settings.

    Here's the spec page:
    The RAM expansion slots accept 184-pin DDR SDRAM DIMMs that are 2.5 volt, unbuffered, 8-byte, nonparity, and DDR400-compliant (PC3200).

    DDR333 (PC2700) or slower DIMMs do not work in the Power Mac G5 computer.

    DIMMs with any of the following features are not supported in the Power Mac G5 computer: registers or buffers, PLLs, ECC, parity, or EDO RAM.

    Mechanical Specifications

    The mechanical design of the DDR SDRAM DIMM is defined by the JEDEC specification JESD21-C, MODULES4_20_4, Release 11b. To find this specification on the World Wide Web, refer to ñRAM Expansion Modulesî .

    The maximum height of DIMMs for use in the Power Mac G5 computer is 2 inches.

    Electrical Specifications

    The electrical design of the SDRAM DIMM is defined by the JEDEC specification JESD21-C, MODULES4_20_4, Release 11b. To find this specification on the World Wide Web, refer to ñRAM Expansion Modulesî .

    The Serial Presence Detect (SPD) EEPROM specified in the JEDEC standard is required and must be set to properly define the DIMM configuration. The EEPROM is powered on 3.3 V. Details about the required values for each byte on the SPD EEPROM can be found on pages 68?70 of the JEDEC specification.
    Important

    For a DIMM to be recognized by the startup software, the SPD feature must be programmed properly to indicate the timing modes supported by the DIMM.

    DIMM Configurations

    The largest DIMM supported is a two-bank DIMM of 1 GB using 512 Mbit DDR SDRAM devices. The maximum number of devices per DIMM is 16.
    Important

    Power is delivered to the Power Mac G5 during sleep mode, so do not remove DIMMs while in sleep mode. A red light adjacent to the DIMM is illuminated when the duct door is removed and power is present.

    Table 4-1 shows information about the different sizes of DDR SDRAM devices used in the memory modules. The memory controller supports 64 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit DDR SDRAM devices. The device configurations include three specifications: address range, word size, and number of banks. For example, a 1 M by 16 by 4 device addresses 1 M, stores 16 bits at a time, and has 4 banks.

    The first column in Table 4-1 shows the memory size of the largest DIMM with that device size that the computer can accommodate. The third column specifies the number of devices needed to make up the 8-byte width of the data bus. The fourth column in the table shows the size of each bank of devices, which is based on the number of internal banks in each device and the number of devices per bank.
    G5 Memory Specs Apple KB #86414
    Apple's PDF on G5 Memory

    Lots of chatter over at Apple forums about this,
    Apple Discussions: biggest thread on G5 memory
    molṑn labe'
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--Ben Franklin

  10. #10
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    Lightbulb Memory Management in OS X

    Introduction to Memory Performance
    Apple Developer Notes

    Memory Management in Mac OS X

    Efficient memory management is an important aspect of writing high performance code in Mac OS X code. Tuning your memory usage can reduce both your application’s memory footprint and the amount of CPU time it uses. In order to properly tune your code though, you need to understand something about how Mac OS X manages memory.

    Unlike earlier versions of Mac OS, Mac OS X includes a fully-integrated virtual memory system that you cannot turn off. It is always on, providing up to 4 gigabytes of addressable space per process. However, few machines have this much dedicated RAM for the entire system, much less for a single process. To compensate for this limitation, the virtual memory system uses hard disk storage to hold data not currently in use. This hard disk storage is sometimes called the “swap” space because of its use as storage for data being swapping in and out of memory.
    Note: Unlike most UNIX-based operating systems, Mac OS X does not use a preallocated swap partition for virtual memory. Instead, it uses all of the available space on the machine’s boot partition.

    The following sections introduce terminology and provide a brief overview of the Mac OS X virtual memory system. For more detailed information on how the Mac OS X virtual memory system works, please see Inside Mac OS X: Kernel Programming.

    Performance: Managing Memory

  11. #11
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    Lightbulb DFA result

    These are the DFA results:

    Model: PowerMac3,4
    PowerMac G4 (Digital Audio)
    DIMM0/J21
    DIMM configured for 512MB
    8008040D0A02400001755400800800018F04060101000E7054 0000140F142C40
    15081508000000000000000000000000000000000000000000 00000000001294
    00000000000000000000000000000000000000000000000000 00000000000000
    00000000000000000000000000000000000000000000000000 000000000064F5
    7.5ns PC133-233
    DIMM checks out OK

    DIMM1/J22
    DIMM configured for 256MB
    8008040D0A01400001755400820800010F04060101000E7554 00000F0E0F2A40
    15081508FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFF12F3
    C1494E46494E454F0836345633323330304755374420202020 20200332025108
    A3D12CFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFF64AF
    7.5ns PC133-222
    DIMM checks out OK

    DIMM2/J23
    DIMM configured for 256MB
    8008040C0A02400001755400000800018F04060101000EC090 0000140F142C20
    15081508000000000000000000000000000000000000000000 0000000000127F
    7F7FB5FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFF011E19
    9D6700FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF FFFFFFFFFF64FF
    7.5ns PC133-333
    DIMM checks out OK

    DIMM3/J24
    DIMM not configured
    no DIMM present

    All your DIMMs checked out OK

    You've gotta love these machines! I don't have OS 9 installed so I ran DFA from the install CD and saved it as a Text Edit file in my Panther User Doc's folder, and voila! there it is in OS X. I knew I had this 222/223/333 mix, but it's all 7.5ns PC133 and didn't think it would be a problem, but maybe it is.

    I'll run DU from the install CD next and see what gives.

    Single User definitely hangs once the CLI screen has finished opening, sometimes the prompt is D.O.A. and sometimes I can enter a few characters before it freezes, but freeze it does.

    A hosed OS seems likely, and that's easy enough to fix, but it does beg the question "Why?"

    The other symptom which persists has to do with logging in as ">console".
    If I try that after a normal boot, the CLI goes to a clear blue screen shortly after appearing. If I try it in Safe Boot, it works OK. I just ran Memtest for 12 hours using that method. But...

    After running through 6 sequences with all OK results, testing 945MB of 1024, I quit and ran it again, and this time it locked down 950MB. So I quit and ran it again; this time it locked 970MB, but then went loopy with the constantly scrolling message "WARNING. No physical memory suitable for pageout or reclaim, pageout thread temporarily going to sleep."

    Seems like each time I run Memtest it grabs a bit more RAM until finally it goes unstable. Maybe that has more to do with Memtest than my machine.

    One other symptom, which may be unrelated, is that Help Viewer is hosed too, and not for the first time. In fact, it's hosed in my back-up too, so I've got a ground-up OS install coming anyway.

    biggles.
    "illegitimis non carborundum"

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    Default

    Dear Biggles,

    to me, your RAM seems fine. The Uni-North Memory Controller you have fitted inside your DA, is happy to handle CAS 3 RAM modules (PC133-3xx).
    The only thing I might want to suggest you is to move the DIMMs so as they show in this order:
    1. J21 - PC133-333
    2. J22 - PC133-233
    3. J23 - PC133-222

    And test your machine out.
    That should force the MC to set it's timing programming to suit the worst DIMM spec you have, for all the others too; but, as the other DIMMs bear better specs anyhow, they should take it easely.

    J24 is empty, right?

    IMHO, that memtest won't tell you much else that you already don't know about your DIMMs.

    If you want the full spec breack down, so as to compare it to your systems minimum requirements, while you are handling the DIMMs to shovel them around (if you want to do that), write down the small in-print you can read on those "little, black, bug-like" chips soldered on them, for each module (every DRAM device on each, single module should bear the same in-print).
    Then post that info here back for me to investigate.

    Your other arguments, about OSX stuff, are so very much interesting to me.... I am LEARNING (GREAT!!).

    Let me know.

    Ciao

    Costa

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    Lightbulb

    I shuffled the RAM as you suggested, damned if things don't feel just a bit quicker!

    From the DRAM's I have these data;

    333: S80016LK7TW
    233: NT5SV32M8AT-7K
    222: HYB3YS256800DT-7
    "illegitimis non carborundum"

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    Default

    Dear biggles,

    I apologize for not posting any sooner my reply to you, but I was away for the weekend and had to manage a 10-years old birthday party with some SCREAMING 35-40 kids around.... For a moment I felt like having done 2 rounds in a ring with Mike Tyson.....
    I was exausted.... (Where do they get all that energy from???)

    Now, back to your memory modules.

    233: NT5SV32M8AT-7K
    These DRAM devices are built by a Company named Nanya Technology Corporation, which is one of the Big five world producers of semiconductors and DRAM devices for the computer markets.

    Your specific DRAM device is now considered an EOL (= End Of Life) product by NTC and, according to their specification data sheet, they bear the following main specs:
    • They can clock up to 133MHz, but are also backward compatible to the 100MHz frequency.
    • The 7K items have a CAS Latency @ 133MHz of 2.
    • They have also being tested @ 143MHz with a CAS Latency of 3.
    • They can be programmed by the Memory Controller to run with a CAS Latency of 3 @ 133MHz.
    • They are self refresh at 7.5 ns rate with CAS Latency of 2, and 7.0 ns. rate with CAS Latency of 3.
    • They are unbuffered non ECC.
    • From what I understand, they were last produced on the 2nd. Quarter 2003.

    Glossary:
    • CAS = Column Address Strobe (or Select)
    • Refresh Rate = it consists of these activities:
      1. Identifying each row and column (row address select, or RAS, and column address select, or CAS)
      2. Keeping track of the refresh sequence (counter)
      3. Reading and restoring the signal from a cell (sense amplifier)
      4. Telling a cell whether it should take a charge or not (write enable)
    • Unbuffered = It means that the RAM expansion module bears no additional device between the chipset (Memory Controller) and the physicall memory stored inside the DRAM devices as they communicate. In other words, the expansion module allows direct communication between the Memory Controller and the RAM cells.
    • Non-ECC = It means that the module must be built without the Error Correction Code feature. The ECC feature is a method used to check the integrity of data stored in memory . ECC memory improves data integrity by detecting errors in memory and is more advanced than parity because it can detect both multiple-bit errors and single-bit errors (parity only detects single-bit errors). ECC is typically found in high-end PCs and file servers where data integrity is key.

    The above is a high quality SDRAM module.

    222: HYB39S256800DT-7
    You have erroneusly transcribed HYB3Y.... Should have been a "9".
    This DRAM devices are built by a Company called Infineon Technologies AG, which is the n° 3 biggest DRAM producer in the world.

    Your specific DRAM device is still in production by Infineon and, according to their specification data sheet, they bear the following main specs:
    • They can clock up to 133MHz, but there are no tests showing they are backward compatible to the 100MHz frequency.
    • The 7 items have a CAS Latency @ 133MHz of 2.
    • They have also being tested @ 143MHz with a CAS Latency of 3.
    • They can be programmed by the Memory Controller to run with a CAS Latency of 3 @ 133MHz.
    • They are self refresh at 7.5 ns rate with CAS Latency of 2, and 7.0 ns. rate with CAS Latency of 3.
    • They are unbuffered non ECC.


    These are also excellent quality DRAM devices.

    333: S80016LK7TW
    For this last DRAM device I have found no details. It is NOT produced by any of the Big names. The only possibility is that it is a Powerchip Semiconductor Corp. product, as their site does not provide any information about their part numbers....
    Otherwise, the above part number does NOT match any of the other big producers.

    Quote Originally Posted by biggles
    Am I right in thinking that the first number in CAS (Column Address Strobe) is the Clock Latency (CL) which describes how many clock cycles for the DIMM to respond to the MC, and the other two are Row Address Strobe (RAS) and RAS precharge time which describe how data are managed within the DIMM? And is it the case that the MC uses all three numbers of whatever's in J21 to control the DIMM's?
    Yes, to your first question.
    Almost there...., to your second question: the 2nd number represents the number of additional clock cycles the DRAM device takes to react to the Memory Controller's request of a RAS pre-charge; the 3rd number represents the number of additional clock cycles the DRAM takes to react to a write(/refresh) command by the MC.
    Mmmm.... yes, in simple terms is correct: the MC will set it's own clock signal on the J21 DIMMs parameters. In your case, it is making it easier for all the remaining DIMMs to "answer" in time to the MC.

    How is it going now your DA? Better?

    Hope you can make good use of the above specs.

    Ciao.

    Costa

    P.S.: If you run DFA now, what does it tell you about your SDRAM modules?

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    Default SpecTek - RAM vendor

    This post is actually a way to complete an answer for Biggles.

    In another thread, Biggles was asking me to find for him the specification data sheet for DRAM devices bearing the S80016LK7TW, which were soldered on a SDRAM module fitted inside his DA, returning him Latency values of 3-3-3.

    After some diggin' around, I came to the knowledge of another SDRAM vendor going by the name of SpecTek, which is a Company part of the Micron Technology, Inc. Group.

    From their web site, I have been able to retrive the very specification data sheet (".PDF" file download) for those DRAM devices, from which I am now able to confirm the following minimum details:
    • The part # S80016LK7TW has been substitued, since December 4th., 2004, into part # SAA16M8Y95AL4TW-75A.
    • The -75A items are PC133 compliant and, at that frequency, bear Latency values of 3-3-3.
    • The DRAM devices are built to 128Mbit density; it means that to make a 256MB SDRAM module, you need 16 of those, 8 on each side.
    • They are 3.3 Volts compliant and capable of an Auto Refresh sequence within 60 ns (3-3-3 + 1 clock cycle to the "ACTIVE" command period). The refresh sequence handles 4,000 RAM cell pages at a time. (This data is normal for a 133MHz compliant device).
    • The following is the new part # symbolism break-down:
      1. SAA = SpecTek Memory
      2. 16M8 = Configuration: 4 MBit RAM cell layers x 8 bit depth x 4 stacking layers (banks) = 32Mbit x 4 = 128Mbit.
      3. Yx5x = Design ID (it should be a physicall attribute, non-electrical)
      4. L4 = 3.3 Volt, Auto Refresh, 4K refresh (see above).
      5. TW = DRAMs built for a TSOP fitting, with 54-pins.
      6. -75A = PC133 (3-3-3) - See above.
    • They are compatible with Clock Cycle Timing of 7.5 ns
    • They are fully programmable and unbuffered.
    • They are Low Voltage TTL compatible, which is good for reliability and a typical characteristic of Micron based semiconductors.

    All in all, such DRAM devices are of a good, solid standard, though you should not pretend from them exceptional performance as from other Micron products.

    SpecTek is based at the Micron plant in Idaho and their Reliability testing takes place in burn-in ovens, a technology proprietary to Micron.

    This so as to be complete.
    Costa
    ________________________

    Ab ovo usque ad mala

  17. #17
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    Lightbulb B&W RAM specs demistified....

    Dear AdaMac,

    Quote Originally Posted by AdaMac
    It was the rerence to speed code that got me wondering about what ram I have now. I understand that 2-2-2 speed codes are to be used for maximum performance. Does DFA tell the speed code? to me it looks like I have 3-3-3, which is not listed in the apple article.
    The Latency values: 3-3-3 vs. 2-2-2, do NOT represent RAM speed code.
    They just represent a TIMING code the Memory Controller fitted on your motherboard *CAN* use with that particular SDRAM module.

    Let me do an example.
    The Latency value of a SDRAM module expresses the number of Memory Bus clock cycles it will take to complete a refresh sequence.
    As you know, Syncronous Dynamic RAM needs to be "refreshed" continuosly, otherwise it will loose quickly all "data" stored onto the RAM cells.
    SDRAM modules are made up by DRAM devices.
    DRAM devices are those little, black, bug-like chips soldered onto the green TSOP module, with 54 "legs", 27 on each side. It's inside those "little buggers" that the real technology resides.
    If you were to open-up one of those DRAM devices and you were to magnify it under a microscope, you would see a very dense and very thin array of semiconducting material, making up a "grill" looking very much like your square-sheet note pad.
    The crossing of every column with a row, represents a single RAM cell (or RAM address).
    Such "cells" can be charged (with SDRAM modules you use 3.3 volts on average), by the Memory Controller. If a cell is charged, when read it will return a binary "1" symbol. If it is not, then it will return a binary "0" symbol.
    A cell looses automatically it's charge after 60 ns (ns = nano seconds, or 1,000,000th of a second), if run on a bus clocking at 133MHz, and after 90ns, if run on a bus clocking at 100MHz.
    So, the refresh sequence is continuosly performed and consists in:
    1. Identifying each row and column (row address select, or RAS, and column address select, or CAS).
    2. Keeping track of the refresh sequence (counter).
    3. Reading and restoring the signal (or charge) from a cell (sense amplifier).
    4. Telling a cell whether it should take a charge or not (write enable).

    A Latency value of 3-3-3, means that the SDRAM module (at the frequency the value refers to) will take:
    1. 3 Memory Bus clock cycles to identify each column address select (CAS).
    2. During the above activity will ALSO keep track of the refresh sequence (counter).
    3. 3 Memory Bus clock cycles to "refresh" a charge on a cell (if it needs to) - (sense amplifier).
    4. 3 Memory Bus clock cycles to tell a cell, which has no charge, to take a new charge - (write enable).

    In your case, at 133MHz, as each clock cycle will take 7.5 ns to happen, the whole refresh sequence will last: (7.5ns x 3) + (7.5 ns x 3) + (7.5 ns x 3) = 67.5 ns. *BUT* the DRAM devices will return an ACTIVE READY signal to the memory controller after 60 ns. to "tell" they are ready for the next instruction.
    If you had a SDRAM module capable of a Latency value of, say, 2-2-2 at 133MHz, the whole refresh sequence would last 45 ns.
    You would thus save 22.5 ns each sequence. In any event, it's a time difference the human body cannot detect.

    The important thing about your RAM modules is that they can performe at 100MHz, as your B&W Memory Bus clocks at that frequency.
    You will find that your SDRAM modules are "backword" compatible to the PC100 specification (100MHz) and, also, that they can handle refresh sequences at 125MHz (i.e.: with 8ns intervals) if and when the Memory Controller needs it.
    BTW, it's the Memory Controller which is in charge of the Memory Bus frequency(ies).

    So, you need to look for SDRAM modules capable of running safely at 100MHz (PC100 - even if backward compatible from a PC133 standard), with a Latency value of 2-2-2 at 100MHz and capable of handling refresh sequences with 8ns. intervals.

    Post back if you don't understand.

    All the best.

    Costa

  18. #18
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    Lightbulb laptop RAM

    Quote Originally Posted by kaps
    ...I have two iBooks (G3/700 and a G3/600, both 12")....
    - How do I find out the other specs of the RAM? On the RAM itself, there is a sticker that says: 512M PC133 SDRAM; S/N 100790-0558....
    Your iBooks are either Late 2001 or Mid 2002 releases, or both. The main differences between the Late 2001 model and the Mid 2002 model are:
    • Graphic card - ATI Rage Mobility (2x AGP) vs ATI Mobility Radeon (2x AGP).
    • VRAM (Video RAM) - 8 MB vs. 16 MB
    • Optical Drive - Choice between CD-ROM, DVD-ROM, CD-RW or "Combo" CD-RW/DVD-ROM vs. "Combo" CD-RW/DVD-ROM, only.
    • Standard Hard disk: 15GB in size vs. 20 GB (though, the Late 2001 iBook, in the "Combo" optical drive configuration, sported a 20GB internal HDD, too).

    However, they both shared the same RAM SO-DIMM specifications; you should thus look for SO-DIMMs bearing the following minimum SDRAM devices specs:
    • PC100 or faster (provided they are backward compatible to the PC100 one; i.e., they can safely be runned at 100MHz frequency).
    • CAS Latency of 2 with an access timing of 7ns (ns = nanoseconds) or less.
    • Burst length must be at least of 4 pages (i.e.: when the internal Memory Controller is querying the SDRAM devices, these must show 4 pages of RAM addresses within the first memory bus clock cycle - a quite normal specification).
    • 3.3 volts compliant (it means that the Memory Controller will use such voltage to "write" onto the RAM address).
    • 256Mbits maximum density (it means that the maximum capacity SO-DIMM you can fit, is 512MB emplying 16 (S)DRAM devices - which are those small, black, bug-looking chips soldered on the SO-DIMM module - 8 on each side).

    If on your iBook/700 there is already implemented a SO-DIMM bearing better specifications than the two new ones you have purchased, it could be a possibility that the Memory Controller is unable to address them correctly, due to the fact that, upon boot, it reads the timing specifications from the SO-DIMM fitted in the first RAM expansion slot. As these are better than the ones you have installed in the 2nd slot, then it could be that the MC has difficulties in addressing RAM cells correctly on the other SO-DIMM, thus returning a "zero" reading.
    I don't know the iBook that well, but see if you can swap the SO-DIMMs around the 700MHz model.
    Quote Originally Posted by kaps
    ...- I didn't zap the PRAM yet. I'll give that a try. (The computer currently isn't in front of me.)

    - How do a do a open firmware reset?...
    Use these links to performe correctly the:
    • PRAM resetting, and
    • Open Firmware NVRAM reset. To access the Open Firmware mode, upon booting your iBook, keep depressed the < COMMAND > + < OPTION > + < O > + < F > keys simultaneously, until you get to a white screen with the flashing pointer and a typed message saying: "To continue booting, type 'mac-boot' and press return".


    PowerBooks/iBooks unresponsive after sleep
    RAM appears to be the culprit:

    "I have a PowerBook G4 15" 1.25Ghz and attempted to add house-brand RAM from CompUSA. I got two 512MB SODIMMs marked "PC-2100/2700." The RAM caused an initial crash on boot and then a kernel panic, but after that I was able to restart and use the new RAM fine, as long as I didn't put the machine to sleep.
    Kingston recommends PowerBook users turn off processor cycling ('highest performance' rather than 'automatic') for their RAM, and this seemed to help. With 'performance' on highest, I was able sleep the PowerBook and wake normally, but only if it had a power supply connected. If it was forced to run off battery power while asleep, it would not wake up.
    Apparently, for RAM to work in recent PowerBooks, it needs to support a low power sleep state. Most cheap/generic RAM brands don't do this, even though they claim PC2700 status and list the same specifications.
    Kingston, for example, has as least three different models of 'PC2700 SODIMM RAM,' all of which have the same specs but are designed for different models... a similar problem with 3rd party RAM in a 17" PowerBook using PC2100 RAM appeared to work, but always died in sleep.

    After biting the bullet and buying a Samsung 1 GB RAM SODIMM, I've had no problems with sleep."

    PC2700 DDR 200 pin SO-DIMM (backward compatible with PC2100)
    512 MB PC2700 DDR SO-DIMM 512DDR2700SO

    Upgrade for the Apple iBook (G4 1.2GHz)
    1GB ¥ DDR PC2100 ¥ CL=2.5 ¥ Unbuffered ¥ Non-parity
    ¥ DDR266 ¥ 2.5V ¥ 128Meg x 64

    http://www.apple.com/support/ibook/
    iBook Upgrades
    PDF Manual: Adding RAM Customer Installable Parts
    iBook Specification
    iBook Discussions
    ... Crucial's SO-DIMMs use Samsung chips. - Anandtech Mac Memory

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    Lightbulb Yosemite 'Smurf

    I recently upgraded my B/W G3 (Mac OS X 10.3.8) by adding a Sonnet Encore ZIF G4 (1GHz). However, ever since I installed it I have had stability problems. These started with both installations of OS X suffering Kernel panics an refusing to boot up again. With the first installation that this happened to, when I tried to reboot, i got a kernel panic reminiscent of 10.1.x (a scroll of text running up the screen). This was the OS X installation that was on my spare HD, so I just did a clean reinstall of the OS. Then this happened with the install on my main HD. This time when I tried to reboot after the initial crash, I got the standard 10.3.x kernel panic message saying that I needed to restart.

    This time I booted from my DiskWarrior CD and tried to run that on my primary HD. However, DW encountered problems with which it couldn't deal. So, I booted from my SystemWorks 3.0 CD and ran Norton Disk Doctor on the HD. That found Several Major problems (I can't remember what they were now) which it was able to fix after a couple of passes. After this I went back to DW and this time it worked. After this I booted from the OS X.3 install CD and used Disk Utility to repair permissions. After all of this, I tried to restart from the HD with the same result as before, the standard 10.3 kernel panic message came up as the OS was starting. So, I did an archive and install on the primary HD. In both cases, the kernel panics happened very early in the boot up process.

    After having reinstalled the OS, I have not had anymore kernel panics, but I have notice a tendency for several programs to to just freeze up. These programs include Photoshop, Excel and Entourage. When this happens, the force quit option does not work. The only thing that has worked to get the programs working again is to restart the computer. However, sometimes the Finder also freezes and then all I can do is a hard restart. The common factor seems to be that this happens when I have Classic active. So, does anyone know what is going on here or how to fix it?

    Run DIMM First Aid and make sure it is all the same PC100 8 ns CL2 or PC133 and not a mix. That is step one.

    If you had a G3 RAM timing wasn't (as much) of an issue as with a G4.

    OEM RAM on B&W was PC100 10 ns - which is too slow.

    DAta corruption can be result of not using the right RAM, or having a rev 1 and not using a controller for your drives.

    There are no known stable B&Ws using 10 ns running OS X, and the more you open in OS X the more likely it is.

    I had a problem at one point with an app not working, at least OS X will show output in console where it would show up. Replaced the RAM module that would be associated with memory address, and all was and has been well ever since.

    ALL RAM has to be the same CL and type/speed. The Grackle memory controller takes what it finds in J19 RAM slot and uses that for all the RAM, which if mixed, would be wrong.

    Also, run Rember and/or memtest 4.05.

    Ram has to be filled from J19 out to J22.
    You have a real mix of RAM that I would remove and replace. Totally.

    I've dealt with RAM and problems helping others over the last 6 yrs.
    You might want to read what I and others have written over on
    Apple Blue and White Discussions about RAM.

    Yosemite SDRAM from Crucial
    Mixing PC100 and PC133
    Power Macintosh G3 (Blue and White): RAM Specifications
    Understanding bandwidth and latency
    Kingston Memory Guide
    http://www.datamem.com/
    www.pc100.com
    Micron SDRAM
    MacGurus Memory Reference
    MacGurus Yosemite SDRAM (old but still good info)
    MacGurus RAM - half-way down the page. 256MB $48.
    MacIntouch: BAD RAM report

    People with of matched (identical) DRAM in B&W have solid stable systems,
    no errors. Wrong or "bad" RAM can cause data corruption.
    I would suggest 512MB or 1024

    A G4 has the ability to push memory at 164MB/sec. Solid. The G3 would begin at 99MB/sec but fall off to 85MB/sec. So G4 requires better quality and higher standards. The B&W always required memory to run at 125MHz (which translates into 8 ns). Some PC133 memory works in 100 MHz front side bus.

    Jaguar would only allocate 128MB to Classic. Panther will try to allocate 256MB (and both will "allocate" 1GB of virtual). OS X "kernel" needs about 80MB is all. As you opened apps, some will load into "high" memory and some will get stacked into other regions. 512MB RAM on B&W seems to be a good basic amount, more of course is "better" and what is important is to get the same RAM so they all "talk" at the same speed so no one "trips" or drops the ball (so to speak).

    Originally, there just wasn't anything except SDRAM at 10 ns at the time, and 8.5/.6 were not pushing it (in fact a G3 only pushes memory at about 85MB/sec after loaded and running, and 99MB/sec on boot) but a G4 will push it at 1.6x the bus speed so the original G3/300s weren't a problem (and we all thought it was a bug in OS 8.5.1 or MSIE 4.0-5 that was the root cause).

    Because memory problems can lead to data corruption and other problems, symptoms and yet "it boots" etc (some of us weren't so lucky and were greeted with kernel panics) you may need to be careful that the system is "clean."

    Even 10.3.8 has changed somewhat how "inactive" memory is treated and handled that can show up as new problems, which can affect users in various ways. But quality RAM should not have any trouble now or even with Tiger, but sometimes a particular application can trigger memory errors with marginally acceptable memory.

  20. #20
    Join Date
    Jan 2001
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    Lightbulb Beige G3 MT/Desktop Models

    You can use the PC100/133 we sell which are 256MB and correct for your system.

    Beige G3/All in One G3/B&W/Yikes G4. 32x4 build, 8 NS, CL2
    256 MB PC100/PC133 DIMMS H256G3-133 $48.00
    http://www.macgurus.com/productpages/ram/mgram.php
    PC100 DIMM 168 pin 3.3v SDRAM low profile 32x4 build for 66 and 100 MHz bus G3 and G4 models Beige, All in One, B&W, Yikes-PCI Graphics G4
    Note: This is the correct 125 MHz (8NS) RAM designed to run perfectly in the Beige, AIO, B&W and Yikes .

    You can determine your RAM with DIMM First Aid:
    http://www.macupdate.com/info.php/id/5714

    let me summarise:

    • What Crucial has to say about upgrading different Beige G3 revision machines, is now out of date.
    • In short, whatever revision ROM/Logic Board Beige G3 you have, it will *NOT* inhibit your ability to increase/upgrade your RAM availability.
    • The ROM/Logic Board revision issue is totally indipendent from the relationship there is between your internal Memory Controller and your RAM banks. See this post of mine for further details.

    You can safely fit inside your Beige Desktop Crucial's 256MB sticks an all three RAM expansion rails, thus maximazing your RAM up to 768MB.
    I have only the following reccomendations:
    1. Make sure you buy the "LOW PROFILE" modules, otherwise you will be unable to close safely your Desktop case as the top of the modules will nock on your internal PSU metal cover. You need to choose those modules with maximum hight = 1.125 in. (or 28.58 mm.). However, Crucial knows which kind will suit you.
    2. Crucial will offer you the PC-100, CL2 (9 ns) ones, which are Micron's part # MT16LSDT3264A-10E; they will be just fine for you. Such modules will ALSO allow you, should you want so, to upgrade your CPU and do a Front System Bus overclocking up to 83.33 MHz (from the stock 66.67MHz).
    3. Remember to flash your PRAM, on first re-booting your Mac after having added your new RAM sticks, so as to let your machine "know" about the new RAM availability.
    4. If you max out your RAM up to 756MB, you will notice at first, that your old Beige will take a few minutes longer to boot into the OS splash screen: this is due to the fact that your internal Memory Controller takes a few minutes longer to performe his Memory Test thing during the booting sequence. You can disable the Memory Test at startup, if so you wish, by opening the Memory Control Pannel while you keep the Option+Control keys pressed; an extra window will open up giving you the ability to choose such disabling feature.


    If you want to know which version Beige G3 you have, even under OS 8.1 System Profiler there should be a section under the "Main System" tab, towards the bottom of the page, regarding the ROM version number: compare your numbers to the ones I have provided you with the above link to my old post. You should be fine with some additional RAM.

    Original question:
    I gather from your question that what you will need from it, is some sort of backup system for your small graphic studio. I thus gather that the main "mean" machine with which you plan to do the "muscle" jobs is a different one? Maybe a more recent G4 or even a newer G5?

    I understand your need for fast disk access, due to the very graphic work you want to do, but... keep in mind that the old Beige G3 motherboard bears the limitation due to it's internal PCI bus, which is capable of 32-bit wide addressing at a maximum clock rate of 33.33MHz. It thus translates into a maximum data throughput of 132MB per second.

    Reguardless the kind of disk controller you are going to fit into it (wheather SCSI, Ultra ATA or SATA), that's the maximum data throughput you can reasonably expect from a hard disk connected to a third party PCI controller card.

    The on-board ATA/IDE bus, is, at best, an ATA/ATAPI-4 standard capable of handling Ultra DMA Mode 0; these are it's main specs:
    • Maximum data burst throughput: 16.7 MB/sec.
    • Supports ATA Packet Interface devices (ATAPI = CD-ROMs, ZIP Drives, etc.).
    • Allows system booting from the ATAPI device.
    • It came with two buses: one for the hard disk and the other for the ATAPI device.
    • It supports modern 80-conductors ATA interface cables (40-signal wires + 40-signal separating wires [earthing] to reduce cross-talking effects due to the increased data rates).

    Depending on the ROM revision mounted on board of your Beige motherboard, this ATA/IDE interface will or not will handle a Master/Slave configuration on its buses:
    1. Revision A ROM (from System Profiler, code # $77D.40F2) = will only support single Master devices; no "Slave" device will be recognized by the system.
    2. Revision B ROM (from System Profiler, code # $77D.45F1) = will allow Master/Slave configurations on the ATA/IDE buses.
    3. Revision C ROM (from System Profiler, code # $77D.45F2) = besides allowing M/S ATA configurations, adds some minor PCI protocols compatabilities.

    OEM SCSI bus installed on the Beige systems from Apple, allows you a 50-pin internal connection and a 25-pin external D-type connections, for a maximum data throughput of 5 MB/sec. (useless, for today's standards).

    The only Apple branded internal SCSI PCI card which was, at the time, available for the Beige G3 series, was the "Apple Single-channel U1 SCSI card", which, if I am not mistaken, was built to the Ultra SCSI protocol and was capable of returning a maximum of 20 MB/sec data throughputs. It's also called "narrow" Ultra SCSI as it uses a bus width of 8-bit and connects to 50-pin devices. Does your IBM SCSI drive use such 50-pin internal connection?

    If it uses a 68-pin connection, then the card is a Wide Ultra SCSI standard and you can use more modern SCSI hard disks with it. However, hard disk data throughput will be limited to a maximum of 40 MB/sec (16-bit width per 20 MHz).

    I am sure that there are people on this very forum who will tell ALL about SCSI in a Beige system. However, be prepared to cough up some serious dough....

    My suggestion is to do a little upgrading but, although the old Beige machines still are capable of doing their job, I would be against spending too much money on it, due to the technical limitations inbuilt into the architecture of the motherboard itself. That would leave you more money for upgrading a more modern system, which, ultimately, could benefit more from your investment.

    I would limit my upgrades to:
    • RAM = Max it out: 3 sticks, 256 MB in size each, 16 DRAM devices on them (8 on each side), PC-100, CAS-2, unbuffered, 8ns refresh rate or better.
    • Hard Disk(s) = Drop a nice, fat, cheap, 120 GB Ultra ATA drive (*) on your internal IDE bus, like this one here, with 8MB of disk cache buffer.
    • Install on it OSX, keeping in mind that you will need to make a 1st partition no larger than 8GB in size, otherwise OSX installer won't recognize it as a suitable disk partition (due to a limitation in-built in the ATA/ATAPI-4 BIOS, on your internal IDE chip).
    • Use the rest of the disk space to record your backups.
    • Drop into one of your free PCI slots a SATA controller card, like Seritek.
    • Place two nice, fat & reliable SATA drives in the spare 3.5" expansion bays you have on the front, like these Seagates, and connect them to your internal SATA card. Place another OSX installation on one of them (the card allows bootable hard disks on it) and use the rest of the space to instal your main applications. Use the other as your main scratch disk.
    • Don't spend $400.00 + on a CPU upgrade for the Beige; IMHO, it isn't worth it. In your shoes, I would rather consider either the Sonnet Encore/ZIF G4 - EG4-700-1M-U - at $249.95, or the DayStar XLR8 MAChSpeed 500-600MHz G4 ZIFat just $199.00. In particular, the latter is even more stright forward of an upgrade than the Sonnet one and the price is right.
    • Drop a nice ATI RADEON 9200 PCI graphic in it. If you do graphics and want to use OSX, you will need that.
    • Pull your old CD-ROM and swap it with a nice Pioneer DVR 108: you won't regret it; actually, you'll soon think how the hell you've managed without one till now.
    • Download all the necessary pacthes to run DVD player with your old Beige G3 system under OSX here.
    • On the last free PCI slot, drop a USB/FW combo card, so that you can use all modern peripherals with your old Beige Machine. A good such card to consider, would be the Sonnet Tango 2.0, but there maybe others with a futher good selection to choose from.


    (*) 120 GB is the maximum size hard disk you can place on your older ATA/ATAPI-4 IDE interface; larger in size HDs won't be exploited to their full capacity by the internal IDE BIOS chip.

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